.="ce MAC register structure"n
./"tx_reset"18t"rx_reset"18t"snd_pause_cmd"nX18tX18tX
.+10/"tx_status"18t"rx_status"18t"ctrl_status"nX18tX18tX
.+10/"tx_mask"18t"rx_mask"18t"ctrl_mask"nX18tX18tX
.+10/"tx_config"18t"rx_config"18t"ctrl_config"nX18tX18tX
+/"xif_config"nX
+/"interpktgap0"18t"interpktgap1"18t"interpktgap2"nX18tX18tX
+/"slot_time"18t"minfrmsize"18t"maxfrmsize"nX18tX18tX
+/"pa_size"18t"jam_size"18t"attempt_limit"nX18tX18tX
+/"ctrl_type"nX
+="addr_regs"
.+18,4/X
+,4/X
+,4/X
+,4/X
+,4/X
+,4/X
+,4/X
+,4/X
+,4/X
+,4/X
+,3/X
+="addr_filter"
.+20,3/X
+/"addr_filter_2_1"18t"addr_filter_0"nX18tX
+="hash_table"
+,4/X
+,4/X
+,4/X
+,4/X
+/"nor_col_cntr"18t"fas_col_cntr"18t"ex_col_cnt"nX18tX18tX
+/"late_col_cntr"18t"defer_timer"18t"peak_attempts"nX18tX18tX
+/"rx_frm_cntr"18t"len_err_cntr"18t"align_err_cntr"nX18tX18tX
+/"fcs_err_cntr"18t"rx_cv_cntr"18t"random_no_seed"nX18tX18tX
+/"state_mch"nX
